An efficient method of fault simulation for digital circuits modeled from boolean gates and memories

Donald M. Schuler, Roger K. Cleghorn. An efficient method of fault simulation for digital circuits modeled from boolean gates and memories. In Judith G. Brinsfield, Stephen A. Szygenda, David W. Hightower, editors, Proceedings of the 14th Design Automation Conference, DAC '77, New Orleans, Louisiana, USA, June 20-22, 1977. pages 230-238, ACM, 1977. [doi]

Abstract

Abstract is missing.