M. Shah, D. Nagchoudhuri. BIST Scheme for Low Heat Dissipation and Reduced Test Application Time. In IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006. pages 239-244, IEEE, 2006. [doi]
Abstract is missing.