19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS

Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Amr Elshazly, Nasser A. Kurd. 19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016. pages 330-331, IEEE, 2016. [doi]

@inproceedings{ShenFFNWEK16,
  title = {19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS},
  author = {Kuan-Yueh James Shen and Syed Feruz Syed Farooq and Yongping Fan and Khoa Minh Nguyen and Qi Wang and Amr Elshazly and Nasser A. Kurd},
  year = {2016},
  doi = {10.1109/ISSCC.2016.7418041},
  url = {http://dx.doi.org/10.1109/ISSCC.2016.7418041},
  researchr = {https://researchr.org/publication/ShenFFNWEK16},
  cites = {0},
  citedby = {0},
  pages = {330-331},
  booktitle = {2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016},
  publisher = {IEEE},
  isbn = {978-1-4673-9467-3},
}