A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS - researchr publication bibliographies

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Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Mark Neidengard, Nasser A. Kurd, Amr Elshazly. A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS. IEEE Trans. on Circuits and Systems, 65-I(7):2109-2117, 2018. [doi]

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