A Pipelined Memory Architecture for High Throughput Network Processors

Timothy Sherwood, George Varghese, Brad Calder. A Pipelined Memory Architecture for High Throughput Network Processors. In 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA. pages 288-299, IEEE Computer Society, 2003. [doi]

Abstract

Abstract is missing.