Chun Shiah, C. N. Chang, Richard Crisp, C.-P. Lin, C. N. Pan, C. P. Chuang, H.-L. Chen, S. H. Jheng, T. F. Chang, W. J. Huang, K. C. Ting, Rick Dai, W. M. Huang, Bor-Doou Rong, Nicky Lu. A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems. In 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019. pages 116, IEEE, 2019. [doi]
Abstract is missing.