High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost

Nobutaro Shibata, Yoshinori Gotoh. High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost. IEEE Trans. VLSI Syst., 23(8):1415-1428, 2015. [doi]

Abstract

Abstract is missing.