A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology

Noboru Shibata, Kazushige Kanda, T. Shimizu, J. Nakai, Osamu Nagao, N. Kobayashi, M. Miakashi, Yasushi Nagadomi, Takeshi Nakano, T. Kawabe, T. Shibuya, Mario Sako, Kosuke Yanagidaira, Toshifumi Hashimoto, H. Date, Manabu Sato, T. Nakagawa, H. Takamoto, Junji Musha, Takatoshi Minamoto, M. Uda, Dai Nakamura, K. Sakurai, T. Yamashita, J. Zhou, R. Tachibana, Teruo Takagiwa, Takahiro Sugimoto, Mikio Ogawa, Yusuke Ochi, K. Kawaguchi, Masatsugu Kojima, T. Ogawa, Tomoharu Hashiguchi, Ryo Fukuda, M. Masuda, K. Kawakami, T. Someya, Yasuyuki Kajitani, Yuuki Matsumoto, Naohito Morozumi, Jumpei Sato, Namas Raghunathan, Y. L. Koh, S. Chen, J. Lee, Hiroaki Nasu, Hiroshi Sugawara, Koji Hosono, Toshiki Hisada, T. Kaneko, H. Nakamura. A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology. In IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019. pages 210-212, IEEE, 2019. [doi]

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