The following publications are possibly variants of this publication:
- Power-Aware Compiler Controllable Chip MultiprocessorHiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara. ieicet, 91-C(4):432-439, 2008. [doi]
- Performance Evaluation of Compiler Controlled Power Saving SchemeJun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara. ishpc 2008: 480-493 [doi]
- Compiler Control Power Saving Scheme for Multi Core ProcessorsJun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara. lcpc 2006: 362-376 [doi]