A Power Efficient Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks

Suhas Shivapakash, Hardik Jain, Olaf Hellwich, Friedel Gerfers. A Power Efficient Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks. In IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020. pages 1-5, IEEE, 2020. [doi]

Abstract

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