High-speed arithmetic coder/decoder architectures

Gireesh Shrimali, Keshab K. Parhi. High-speed arithmetic coder/decoder architectures. In IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '93, Minneapolis, Minnesota, USA, April 27-30, 1993. pages 361-364, IEEE Computer Society, 1993. [doi]

Abstract

Abstract is missing.