Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs

Roberto Sierra, Carlos Carreras, Gabriel Caffarena. Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs. In 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, Platja d'Aro, Spain, July 2-4, 2018. pages 7-12, IEEE, 2018. [doi]

Abstract

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