Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, Debasish Behera. A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay. In Rakesh Patel, Tom Andre, Aurangzeb Khan, editors, 2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011. pages 1-4, IEEE, 2011. [doi]
Abstract is missing.