Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy. Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. In Enrico Macii, Vivek De, Mary Jane Irwin, editors, Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001. pages 267-270, ACM, 2001. [doi]
Abstract is missing.