A ring-VCO-based sub-sampling PLL CMOS circuit with -119 dBc/Hz phase noise and 0.73 ps jitter - researchr publication

researchr

You are not signed in
Sign in
Sign up

Kenta Sogo, Akihiro Toya, Takamaro Kikkawa. A ring-VCO-based sub-sampling PLL CMOS circuit with -119 dBc/Hz phase noise and 0.73 ps jitter. In Proceedings of the 38th European Solid-State Circuit conference, ESSCIRC 2012, Bordeaux, France, September 17-21, 2012. pages 253-256, IEEE, 2012. [doi]

Abstract is missing.

runs on WebDSL