A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique - researchr publication

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Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim. A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. IEEE Trans. VLSI Syst., 25(1):344-353, 2017. [doi]

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