Patri Sreehari, Pavankumarsharma Devulapalli, Dhananjay Kewale, Omkar Asbe, K. S. R. Krishna Prasad. Power optimized PLL implementation in 180nm CMOS technology. In 18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, India, July 16-18, 2014. pages 1-2, IEEE, 2014. [doi]
Abstract is missing.