Aswin Sreekumar, Bolupadra Sai Shankar, B. Naresh Kumar Reddy. Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability. Integration, 100:102282, 2025. [doi]
@article{SreekumarSR25,
title = {Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability},
author = {Aswin Sreekumar and Bolupadra Sai Shankar and B. Naresh Kumar Reddy},
year = {2025},
doi = {10.1016/j.vlsi.2024.102282},
url = {https://doi.org/10.1016/j.vlsi.2024.102282},
researchr = {https://researchr.org/publication/SreekumarSR25},
cites = {0},
citedby = {0},
journal = {Integration},
volume = {100},
pages = {102282},
}