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Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor

Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann. Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. In Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999. pages 414-420, IEEE Computer Society, 1999.

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