Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor

Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann. Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. In Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999. pages 414-420, IEEE Computer Society, 1999.

Authors

Manfred Stadler

This author has not been identified. Look up 'Manfred Stadler' in Google

Thomas Röwer

This author has not been identified. Look up 'Thomas Röwer' in Google

Hubert Kaeslin

This author has not been identified. Look up 'Hubert Kaeslin' in Google

Norbert Felber

This author has not been identified. Look up 'Norbert Felber' in Google

Wolfgang Fichtner

This author has not been identified. Look up 'Wolfgang Fichtner' in Google

Markus Thalmann

This author has not been identified. Look up 'Markus Thalmann' in Google