Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor

Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann. Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. In Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999. pages 414-420, IEEE Computer Society, 1999.

@inproceedings{StadlerRKFFT99,
  title = {Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor},
  author = {Manfred Stadler and Thomas Röwer and Hubert Kaeslin and Norbert Felber and Wolfgang Fichtner and Markus Thalmann},
  year = {1999},
  tags = {rule-based},
  researchr = {https://researchr.org/publication/StadlerRKFFT99},
  cites = {0},
  citedby = {0},
  pages = {414-420},
  booktitle = {Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999},
  publisher = {IEEE Computer Society},
}