Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs

Luca Sterpone. Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs. In Jürgen Becker, Roger Woods, Peter M. Athanas, Fearghal Morgan, editors, Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings. Volume 5453 of Lecture Notes in Computer Science, pages 85-96, Springer, 2009. [doi]

Abstract

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