Scalable FPGA graph model to detect routing faults

Luca Sterpone, Gianpiero Cabodi, S. F. Finocchiaro, Carmelo Loiacono, F. Savarese, Boyang Du. Scalable FPGA graph model to detect routing faults. In 22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, Sant Feliu de Guixols, Spain, July 4-6, 2016. pages 155-160, IEEE, 2016. [doi]

Abstract

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