A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs

Robert J. Stewart, Greg J. Michaelson, Deepayan Bhowmik, Paulo Garcia, Andy Wallace. A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs. In Jesús Carretero, Javier García Blas, Victor Gergel, Vladimir V. Voevodin, Iosif Meyerov, Juan A. Rico-Gallego, Juan Carlos Díaz Martín, Pedro Alonso, Juan José Durillo, José Daniel García Sánchez, Alexey L. Lastovetsky, Fabrizio Marozzo, Qin Liu, Md. Zakirul Alam Bhuiyan, Karl Fürlinger, Josef Weidendorfer, José Gracia, editors, Algorithms and Architectures for Parallel Processing - ICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings. Volume 10049 of Lecture Notes in Computer Science, pages 174-188, Springer, 2016. [doi]

Abstract

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