Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration

Kuniaki Sueoka, Akihiro Horibe, T. Aoki, Sayuri Kohara, Kazushige Toriyama, Hiroyuki Mori, Yasumitsu Orii. Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration. In 2015 International 3D Systems Integration Conference, 3DIC 2015, Sendai, Japan, August 31 - September 2, 2015. IEEE, 2015. [doi]

Abstract

Abstract is missing.