Zhenyu Sun, Xiuyuan Bi, Hai Helen Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu. Multi retention level STT-RAM cache designs with a dynamic refresh scheme. In Carlo Galuzzi, Luigi Carro, Andreas Moshovos, Milos Prvulovic, editors, 44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, 3-7 December 2011, Porto Alegre, Brazil. pages 329-338, ACM, 2011. [doi]
@inproceedings{SunBLWOZW11,
title = {Multi retention level STT-RAM cache designs with a dynamic refresh scheme},
author = {Zhenyu Sun and Xiuyuan Bi and Hai Helen Li and Weng-Fai Wong and Zhong-Liang Ong and Xiaochun Zhu and Wenqing Wu},
year = {2011},
doi = {10.1145/2155620.2155659},
url = {http://doi.acm.org/10.1145/2155620.2155659},
researchr = {https://researchr.org/publication/SunBLWOZW11},
cites = {0},
citedby = {0},
pages = {329-338},
booktitle = {44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, 3-7 December 2011, Porto Alegre, Brazil},
editor = {Carlo Galuzzi and Luigi Carro and Andreas Moshovos and Milos Prvulovic},
publisher = {ACM},
isbn = {978-1-4503-1053-6},
}