Multi retention level STT-RAM cache designs with a dynamic refresh scheme

Zhenyu Sun, Xiuyuan Bi, Hai Helen Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu. Multi retention level STT-RAM cache designs with a dynamic refresh scheme. In Carlo Galuzzi, Luigi Carro, Andreas Moshovos, Milos Prvulovic, editors, 44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, 3-7 December 2011, Porto Alegre, Brazil. pages 329-338, ACM, 2011. [doi]

No reviews for this publication, yet.