Test Architecture for Fine Grained Capture Power Reduction

Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Matan Segal, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar. Test Architecture for Fine Grained Capture Power Reduction. In 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, November 27-29, 2019. pages 558-561, IEEE, 2019. [doi]

@inproceedings{SunJRSNDMB19,
  title = {Test Architecture for Fine Grained Capture Power Reduction},
  author = {Yi Sun and Hui Jiang and Lakshmi Ramakrishnan and Matan Segal and Kundan Nepal and Jennifer Dworak and Theodore W. Manikas and R. Iris Bahar},
  year = {2019},
  doi = {10.1109/ICECS46596.2019.8964790},
  url = {https://doi.org/10.1109/ICECS46596.2019.8964790},
  researchr = {https://researchr.org/publication/SunJRSNDMB19},
  cites = {0},
  citedby = {0},
  pages = {558-561},
  booktitle = {26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, November 27-29, 2019},
  publisher = {IEEE},
  isbn = {978-1-7281-0996-1},
}