A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis - researchr publication

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Savithri Sundareswaran, David Blaauw, Abhijit Dharchoudhury. A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. In 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India. pages 175-180, IEEE Computer Society, 1999. [doi]

Abstract is missing.

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