A Scalable Symbolic Simulator for Verilog RTL

Sasidhar Sunkari, Supratik Chakraborty, Vivekananda M. Vedula, Kailasnath Maneparambil. A Scalable Symbolic Simulator for Verilog RTL. In Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra, editors, Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA. pages 51-59, IEEE Computer Society, 2007. [doi]

Abstract

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