Implementing a Methodology for Formally Verifying RISC Processors in HOL

Sofiène Tahar, Ramayya Kumar. Implementing a Methodology for Formally Verifying RISC Processors in HOL. In Jeffrey J. Joyce, Carl-Johan H. Seger, editors, Higher Order Logic Theorem Proving and its Applications, 6th International Workshop, HUG 93, Vancouver, BC, Canada, August 11-13, 1993, Proceedings. Volume 780 of Lecture Notes in Computer Science, pages 281-294, Springer, 1993.

Abstract

Abstract is missing.