High-speed demonstration of low-power 1 k-bit shift-register memories using LR-biasing SFQ circuits

Toshihiro Takahashi, Ryo Numaguchi, Yuki Yamanashi, Nobuyuki Yoshikawa. High-speed demonstration of low-power 1 k-bit shift-register memories using LR-biasing SFQ circuits. IEICE Electronic Express, 13(6):20160074, 2016. [doi]

Abstract

Abstract is missing.