Yasuhiro Takai, Mamoru Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Yukio Fukuzo, Hiroshi Watanabe. 250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture. J. Solid-State Circuits, 29(4):426-431, April 1994. [doi]
Abstract is missing.