A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion

Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura. A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion. J. Solid-State Circuits, 49(2):471-485, 2014. [doi]

@article{TakemotoYYMTCLTN14,
  title = {A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion},
  author = {Takashi Takemoto and Hiroki Yamashita and Fumio Yuki and Noboru Masuda and Hidehiro Toyoda and Norio Chujo and Yong Lee and Shinji Tsuji and Shinji Nishimura},
  year = {2014},
  doi = {10.1109/JSSC.2013.2291099},
  url = {http://dx.doi.org/10.1109/JSSC.2013.2291099},
  researchr = {https://researchr.org/publication/TakemotoYYMTCLTN14},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {49},
  number = {2},
  pages = {471-485},
}