Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies

Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Kouichi Kanda, Kohtaroh Gotoh, Hideki Ishida, Junji Ogawa. Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies. IEICE Transactions, 89-C(3):300-313, 2006. [doi]

Abstract

Abstract is missing.