PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion

Sachin Taneja, Massimo Alioto. PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion. In 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, September 23-26, 2019. pages 61-64, IEEE, 2019. [doi]

Abstract

Abstract is missing.