Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs. Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations. In René van Leuken, Gilles Sicard, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers. Volume 6448 of Lecture Notes in Computer Science, pages 190-199, Springer, 2010. [doi]
Abstract is missing.