High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories

Toru Tanzawa, Yoshinori Takano, Kentaro Watanabe, Shigeru Atsumi. High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories. J. Solid-State Circuits, 37(10):1318-1325, 2002. [doi]

Authors

Toru Tanzawa

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Yoshinori Takano

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Kentaro Watanabe

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Shigeru Atsumi

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