Toru Tanzawa, Yoshinori Takano, Kentaro Watanabe, Shigeru Atsumi. High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories. J. Solid-State Circuits, 37(10):1318-1325, 2002. [doi]
@article{TanzawaTWA02,
title = {High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories},
author = {Toru Tanzawa and Yoshinori Takano and Kentaro Watanabe and Shigeru Atsumi},
year = {2002},
doi = {10.1109/JSSC.2002.803045},
url = {https://doi.org/10.1109/JSSC.2002.803045},
researchr = {https://researchr.org/publication/TanzawaTWA02},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {37},
number = {10},
pages = {1318-1325},
}