An FPGA-based hardware accelerator for simulating spatiotemporal neurons

Ghaith Tarawneh, Jenny Read. An FPGA-based hardware accelerator for simulating spatiotemporal neurons. In 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, December 7-10, 2014. pages 618-621, IEEE, 2014. [doi]

Abstract

Abstract is missing.