A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin. A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores. J. Electronic Testing, 20(2):155-168, 2004. [doi]

Abstract

Abstract is missing.