Verilog Coding Style for Efficient Synthesis In FPGA - researchr publication

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Himanshu Thapliyal, M. B. Srinivas, Rameshwar Rao, Hamid R. Arabnia. Verilog Coding Style for Efficient Synthesis In FPGA. In Laurence Tianruo Yang, Hamid R. Arabnia, Yiming Li, Salam N. Salloum, José G. Delgado-Frias, editors, Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005. pages 85-90, CSREA Press, 2005.

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