An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz

José A. Tierno, Sergey Rylov, Alexander Rylyakov, Montek Singh, Steven M. Nowick. An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz. In 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK. pages 84, IEEE Computer Society, 2002. [doi]

@inproceedings{TiernoRRSN02,
  title = {An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz},
  author = {José A. Tierno and Sergey Rylov and Alexander Rylyakov and Montek Singh and Steven M. Nowick},
  year = {2002},
  url = {http://csdl.computer.org/comp/proceedings/async/2002/1540/00/15400084abs.htm},
  researchr = {https://researchr.org/publication/TiernoRRSN02},
  cites = {0},
  citedby = {0},
  pages = {84},
  booktitle = {8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-1540-1},
}