A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering

Benjamas Tongprasit, Kiyoto Ito, Tadashi Shibata. A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering. In International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan. pages 2389-2392, IEEE, 2005. [doi]

Abstract

Abstract is missing.