A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering - researchr publication related

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Benjamas Tongprasit, Kiyoto Ito, Tadashi Shibata. A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering. In International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan. pages 2389-2392, IEEE, 2005. [doi]

The following publications are possibly variants of this publication:

A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image ProcessingKiyoto Ito, Benjamas Tongprasit, Tadashi Shibata. tcas, 56-I(1):114-123, 2009. [doi]

A Real-Time Motion-Feature-Extraction VLSI Employing Digital-Pixel-Sensor-Based Parallel ArchitectureHongbo Zhu, Tadashi Shibata. tcsv, 24(10):1787-1799, 2014. [doi]

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