100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet - researchr publication related

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Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Kouji Fukuda, Kouji Nakahara, Hiroaki Nishi. 100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet. IEICE Transactions, 89-B(3):696-703, 2006. [doi]

The following publications are possibly variants of this publication:

A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane ApplicationsHidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Matsuaki Terada. ieicet, 90-C(10):1957-1963, 2007. [doi]

A 400-Gb/s and Low-Power Physical-Layer Architecture for Next-Generation EthernetMasashi Kono, Akihiro Kambe, Hidehiro Toyoda. icc 2011: 1-6 [doi]

A 100 Gb/s and High-Reliable Physical-Layer Architecture for VSR and Backplane EthernetHidehiro Toyoda, Michitaka Okuno, Shinji Nishimura, Matsuaki Terada. icc 2008: 5417-5421 [doi]

A Novel 400-Gb/s (100-Gb/s×4) Physical-Layer Architecture Using Low-Power TechnologyMasashi Kono, Akihiro Kambe, Hidehiro Toyoda, Shinji Nishimura. ieicet, 95-B(11):3437-3444, 2012. [doi]

A 100-Gb-Ethernet subsystem for next-generation metro-area networkHidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Ryouji Yamaoka, Hiroaki Nishi. icc 2005: 1036-1042 [doi]

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