An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs - researchr publication authors

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Shadi Traboulsi, Michael Meitinger, Rainer Ohlendorf, Andreas Herkersdorf. An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs. In Antonio NÃºÃ±ez, Pedro P. Carballo, editors, 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece. pages 11-18, IEEE Computer Society, 2009. [doi]

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