Jeng-Han Tsai, Shao-Wei Huang, Jian-Ping Chou. A 5.5 GHz low-power PLL using 0.18-µm CMOS technology. In 2014 IEEE Radio and Wireless Symposium, RWS 2014, Newport Beach, CA, USA, January 19-23, 2014. pages 205-207, IEEE, 2014. [doi]
Abstract is missing.