The VLSI architecture of a highly efficient configurable pre-processor for MIMO detections

Tzu-Ting Tseng, Chung-An Shen. The VLSI architecture of a highly efficient configurable pre-processor for MIMO detections. In 36th IEEE International Performance Computing and Communications Conference, IPCCC 2017, San Diego, CA, USA, December 10-12, 2017. pages 1-5, IEEE, 2017. [doi]

Abstract

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