Efficient Bit-Level Model Reductions for Automated Hardware Verification

Sergey Tverdyshev, Eyad Alkassar. Efficient Bit-Level Model Reductions for Automated Hardware Verification. In Stéphane Demri, Christian S. Jensen, editors, 15th International Symposium on Temporal Representation and Reasoning, TIME 2008, Université du Québec à Monteéal, Canada, 16-18 June 2008. pages 164-172, IEEE Computer Society, 2008. [doi]

Authors

Sergey Tverdyshev

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Eyad Alkassar

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